1. Field of the Invention
The invention relates to electronic design automation systems, and more particularly to computer-aided engineering tools for logic synthesis.
2. Description of the Background Art
One aspect of integrated circuit design that is critical for circuit performance is the timing of signals between circuit elements. As very large scale integrated circuit (VLSI) fabrication technology reaches submicron device dimensions and circuit speed falls into the sub-nanosecond range, interconnect delays become the dominant factor in determining circuit speed. Further, as integrated circuit designs increase in size, interconnect delays between circuit cells become larger and account for an increasing percentage of total circuit delay. Accurately modeling the delay characteristics of the circuit elements has thus become an increasingly important process during the development of electronic system prototypes.
Currently, the design of electronic circuits and systems employs computer-automated design systems for defining and verifying various prototype circuit configurations. Typically circuit definition is accomplished by graphically entering circuit schematics at an engineering workstation or by using a logic synthesis tool, which generates a high-level, hardware description file functionally describing the logic of the desired prototype circuit. As part of the circuit definition, a number of delay constraints that limit the interconnect delay between circuit elements are specified by the circuit designer. These delay constraints must be satisfied when the prototype circuit is fabricated.
Logic synthesis tools usually include optimization routines, which convert the high-level prototype definition into an intermediate form that is more appropriate for the functional implementation of the prototype in a particular circuit manufacturing technology. Optimization during logic synthesis typically includes two stages: (1) a technology-independent ("TI") stage, where general logic expressions synthesized from the hardware description file are minimized, and (2) a technology-dependent ("TD") stage, where the minimized logic expressions are mapped into target library cells for a specific fabrication technology.
During the TI stage there is much flexibility to restructure circuit logic to minimize the number of nodes and literals, thereby reducing the area of the circuit. During this stage the circuit can be most effectively restructured to meet the specified delay constraints critical for circuit performance. During the TD stage, the delay characteristics of the target library are available, but very little restructuring of the circuit is possible. Accordingly, to meet the timing requirements of the prototype design, it is preferable to restructure the circuit during the TI stage.
However, little accurate delay information is available at the TI stage for optimizing the prototype circuit design with respect to the specified delay constraints. Traditionally at the TI stage, the available delay information is limited to fixed intrinsic delays of boolean nodes, which is the delay during the operation of a logic cell to process its input signals, and fixed resistive-capacitive (R-C) delays (wire delays) for each fan-out from a node, which is the delay of driving the output signal from a node to the next node. Each fan-out is typically fixed at a constant value of 0.2 .mu.sec of delay, so the total delay of a prototype circuit is simply the number of fan-outs times the R-C constant delay value added to a fixed intrinsic delay for each logic stage.
This static timing analysis does not realistically reflect the varying delay contributions that arise once the circuit is mapped during the technology dependent optimization stage. First, traditional static timing analysis does not account for the fact that different target component libraries, e.g. CMOS, NMOS, TTL, all have distinct intrinsic delays for the same logic cell, such as a NAND cell, and distinct R-C delays for fan-outs, or that these delays can differ from the fixed values traditionally employed during the TI stage. Further these different fabrication technologies influence the relative significance of intrinsic delay and the fan-out delay on circuit performance, and hence on the overall delay of the circuit. Thus, TI optimization using static delay models is limited to a generalized optimization that will not fully exploit the timing properties of the target library in order to satisfy the delay constraints of the prototype circuit.
Second, conventional delay models do not reflect the delay characteristics according to the complexity of the boolean nodes of the circuit. Typically static timing models count the number of logic stages, regardless of the number of input signals to each node, or the complexity of the circuit logic, and assign a fixed delay for each logic stage. This type of analysis does not accurately model the differences in timing between complex logic gate networks and simple ones where there are varying numbers of gates in each logic stage that contribute varying amounts of delay. For example, in a static timing analysis the simple gate network (ab+cd+ac) has the same number of logic stages (2) and hence the same delay as the more complex gate network (abcd+cdac+edgf+ahjk), and no account is made of the greater delay typically associated with the larger (4 variables vs. 2 variables) nodes. A static timing analysis that merely counts logic stages is also inaccurate since a gate network with many logic stage each having a small number of literals may be faster than a gate network with fewer logic stages each having a large number of literals.
Finally, conventional delay models do not account for variations in gate fan-in delay, which is the variable timing difference between the input signals into a given gate network. For example, a gate network can have four input signals I.sub.1, I.sub.2, I.sub.3, and I.sub.4 with delays of 2, 2, 7, and 7 respectively, relative to an arbitrary signal. Though input signals I.sub.3 and I.sub.4 arrive later than I.sub.1 and I.sub.2, and thus could be assigned to a later logic stage, optimization using a static timing analysis will not distinguish between the input signals, but treat them all as arriving into the gate network at the same time. Accordingly, it will fail to fully optimize the gate network, and may be unable to satisfy the delay constraints of the network.
It is therefore desirable to provide an improved technique for technology-independent optimization that incorporates a more accurate model of timing delay into the minimized logic expressions than the static timing models currently employed.